Parasitic Insensitive Impedance Boosting with 4-tap FIR
Impedance Boosting Technique 2
Architecture
CTDSM using low noise linear integrator & VCO-based quantizer
Parasitic insensitive impedance boosting with 4-tap FIR
Current recycling OPAMP and chopper stabilization for integrator noise reduction
VCO based quantizer and 2nd order noise shaping for quantization noise reduction
Block Diagram
Performance - SNDR, IRN, CMRR
SNDR(Signal to Noise/Distortion Ratio) : 85.1dB at 1kHz BW
IRN(Input Referred Noise) : 1.4 µV/√Hz at 200Hz(8.5 µV/√Hz at 10kHz)
CMRR(Common Mode Rejection Ratio) : over 82dB
Performance - ZIN
Zin(Input Impedance) : over 421MΩ at DC(147MΩ at 1kHz)
Performance - True ExG Acquisition
